The present invention relates to a circuit for detecting a synchronizing pattern from a code series containing a synchronizing code, and it relates particularly to a synchronizing code detection circuit operating at a low rate of 1/I, I being an integer, of an original bit rate.
When digital codes are transmitted or recorded, a synchronizing code is transmitted or recorded in addition to data so as to facilitate the processing on the reception side. The synchronizing code has a code pattern which is hard to be generated in the data, and based on the synchronizing pattern detected, the data transmitted or recorded bit by bit are converted into a parallel code series word by word or a code block comprising a plurality of words, for instance, on the reception side.
The detection of the synchronizing pattern has been conducted by such a known method to be described below, as is described in the Official Gazettes on Japanese Patent Laid-Open No. 111352/1981 and Japanese Patent Publication No. 2230/1982, for instance.
Assuming that the synchronizing code consists of l bits, received codes are brought into an l bit-shift register, and it is decided whether l bits of the output thereof correspond to the synchronizing pattern, while shifting is conducted by one bit. In other words, this method necessitates a shift register and a correspondence detection circuit. These circuit elements are required naturally to operate at the same rate as that of the received codes.
This causes a problem that a power consumed and a heat generated by the necessary circuit elements are increased as the rate of codes is increased. When the shift register is desired to operate at a rate of about 100 Mb/s, for instance, an ECL (Emitter-Coupled Logic) device is necessitated, and a power consumed thereby is about 40 mW/gate. This power consumption is twenty times larger than that of a TTL (Transistor Transistor Logic) device operating at a low rate. In addition to a problem that packaging of a unit turns difficult, etc., this large power consumption makes it hard to prepare an LSI, etc.
The synchronizing code detection circuit of high rate has a number of problems as described above, and there has been no example in which these problems are settled by using low-rate circuit elements.